This section is intended to provide a background or context to the invention that is recited in the claims. The description herein may include concepts that could be pursued, but are not necessarily ones that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, what is described in this section is not prior art to the description and claims in this application and is not admitted to be prior art by inclusion in this section.
The following abbreviations that may be found in the specification and/or the drawing figures are defined as follows:
eNB E-UTRAN Node B (evolved Node B)
e-MMC embedded multi-media card
FW firmware
HDD hard drive
HW hardware
MLC multi-level cell
Node B base station
OTP one-time programmable
PE program-erase
SLC single-level cell
SW software
UE user equipment, such as a mobile station or mobile terminal
Mobile devices, such as UEs, may use memory for storing user data, for example, music, pictures, applications, maps, etc. The amount of user data stored in mobile devices is increasing and will continue to grow. Some high-end devices provide user data storage based on non-volatile memory such as NAND memory technology (also known as flash memory). NAND memory usage has expanded to mid-range devices.
Many products have more memory included than what is strictly needed for basic usage. People are also using this extra memory on their phones to store critical data, for example, business related data, personal pictures, notes, etc.
One reason for the success of NAND memory is its cost structure. However, due to cost pressures for higher densities, more bits are being stored per memory cell. Storing multiple bits per cell allows a device to hold greater amounts of data at a lower cost structure, but at the expense of the reliability of the cell.
A few parameters affecting NAND memory reliability include:                Manufacturing process used (newer processes allowing small physical dimensions which may have lower reliability)        Number of bits per cell (multiple voltage levels per cell may cause lower reliability)        Number of the times that a memory cell has been rewritten (During a cycle, the cell is erased and rewritten. A higher number of cycles causes lower reliability, e.g., for a floating gate technology there will be more electrons trapped in the insulating layer.)        Time between write and read (retention of cycled memory is lower)        Temperature (NAND retention in high temperatures is lower)        
A NAND memory's reliability may reach levels where heavy use can wear out the device within a few years. An additional challenge for NAND cells is that if a user cycles the memory heavily at the begin of their usage then the memory may no longer be able to store its data for as long a period of time than if the memory cell had been cycled only a few times. Higher data reliability for a NAND based storage device is available when the storage has been cycled a minimum number of times.
The smaller the process used for manufacturing the cell the smaller the physical dimensions are. This results in higher interference between cells as they are closer to each other. Additionally, as there is a thinner insulating material layer around the floating gate electrons may escape easier and fewer electrons will fit into the floating gate. Thus, if even one electron escapes, it represents a higher percentage of the electrons in the cell as compared to previous processes.
Users who do not cycle their data as much might appreciate an option to have increased density available for their non-critical data. For other users the safety of their data is more important.
While it may sound drastic to make a selection between reliability and density, this is what users and manufacturers do when deciding which memory cards to purchase. For example, memory cars that are based on multi-bit per cell technologies may provide greater density. On the other hand, the more bits there are per cell the lower the reliability may be.
For personal computers, a hard drive (HDD) could compress its content for increased density. Such an operation may be performed by software (SW). This technique did not store more data on a hardware (HW) level; rather, the data was packaged at a software level to be smaller image. Additionally, HDD technology may not experience a similar reliability drop due to cycling or storage time to that seen in NAND devices.
Some NAND based memories may have a factory-set option as to which portion of the multi-level cell (MLC) NAND (e.g., where two or more voltage levels are used for one cell value) where is to be used as a single-level cell (SLC) NAND. As a MLC has a lower reliability and performance, using this factory setup, the mass storage can provide improved reliability for one portion of the memory and at the same time performance for this part of the memory is also increased. The cost of this is that the available density is reduced since the portion used as SLC has less density than if it were be used as MLC.
In the eMMC standard, it is possible to set partition characteristics for a memory medium (either for the whole media or for part of it), such as, normal vs. enhanced (which impacts the density) or system data vs. “volatile” data (related to the retention time of the data). This method does not provide flexible scaling as this setting can only be done at the beginning of the usage and it is typically done at the factory.
Another eMMC functionality proposed is dynamic capacity where part of the memory can be defined as available for an eMMC module's internal use. This can include using the cells as additional spare areas, which may extend cycling limits for the rest of the memory. This setting could be done during the lifetime of the eMMC module. This method is based on removing density visible outside the eMMC module for better functionality. However, only removing cells is possible; therefore, the cells removed cannot be returned and made available outside the eMMC module.
In order to mitigate some of the problems caused by memory usage, a wear level process may level cycling over a greater area of the memory. Data stored in the memory is moved to different locations in the memory so that all the cells experience similar cycling levels. The intent is to extend the lifetime of individual cells of the memory; however, at the same time, the reliability of the memory as a whole is also evenly reduced.
Another conventional memory system provides a user configurable density/performance option. Depending on a selectable option, the memory blocks (or a portion of them) are set to MLC (high density with slow performance) or SLC (low density with high performance). However, this conventional memory system does not take into account the wearing of cells due to repeated program-erase (PE) operations.